netgen

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

An open-source static random access memory (SRAM) compiler.

JKU IIC OSIC-Multitool for open-source IC (OSIC) design for SKY130.

Massively Parallel Simulator of Optical Coherence Tomography (OCT-MPS)

Minimal SKY130 example with self-checking LVS, DRC, and PEX

VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW takes contro…

Netgen Enhanced Binary FIle Bundle is an eZ Platform bundle that provides a field type that reimplements ezbinaryfile field type.

A Python module for generating random network flows problem instances in DIMACS graph format.

Design analog ICs tailored to system requirements with a solid grasp of CMOS technology. Gain proficiency in circuit analysis and master tools like ngspice, xschem, Magic, and Python for full custom design and verification.

SAK = Swiss Army Knife - Various scripts and utilities around popular FOSS EDA

An IDE for full RTL to GDSII ASIC design flow, Easier for beginners, Faster for experts, Built for the Open Hardware movement

Clean-room container for building RTL → GDSII: a slim, pinned open-source EDA toolchain (Yosys · Verilator · OpenROAD · Magic · KLayout · Netgen · ngspice + sky130/gf180 PDKs), built from scratch on GitHub Actions and published to GHCR.

Mixed-mode silicon cochlea implementing wavelet processing in 130nm skywater process, embedded in efabless Caravel

A simple study showing eZ Platform content consumed by Gatsby via GraphQL

A Linux-Local Installation of TT tools at version parity with TinyTapeout Selected Versions (see branch name)

EC302-VLSI-Design-Lab

RTL-to-GDSII implementation of an 8-bit UART using Verilog HDL, OpenLane, SKY130A PDK, Yosys, Magic, Netgen, and ModelSim.

This is a standard VLSI cell library that contains custom combinational and sequential cells using Magic VLSI, ngspice simulation, DRC/LVS checks with netgen, and parasitic extractions.

Content visibility scheduling for Ibexa CMS

Conda build for netgen mesher